This invention relates to a manufacturing method of a semiconductor device capable of downsizing the device by planarization and increasing the operation speed of the device by the downsizing and by the use of a silicide forming process.
Minimizing an element region on a semiconductor substrate of a semiconductor device is so advantageous for increasing the integration density of a LSI, increasing the operation speed of the device, and reducing the power consumption, and thus has been eagerly studied for years.
The various studies of increasing the integration density of a LSI, increasing the operation speed of the device, and reducing the power consumption, have been proposed in Jpn. KOKAI Pat. Appln. No. 1-187864, Jpn. KOKAI Pat. Appln. No. 3-76228, Jpn. KOKAI Pat. Appln. No. 5-251458, and so on.
FIG. 4 shows the structure of a bipolar transistor as an example of the semiconductor device according to the conventional technique.
This bipolar transistor has an element-isolating oxide film 102 on the surface of a silicon substrate 101, as shown in FIG. 4. The silicon substrate 101 further has an epitaxial base region 103 and a buffer oxide film 105, which are stacked on a predetermined portion thereof. On the element-isolating oxide film 102, the epitaxial base region 103, and the buffer oxide film 105, a base extension polysilicon 104, an oxide film 107, and a nitride film 108 are stacked in order. Further, the sidewall of the opening formed in the central portion of the device is provided with a sidewall nitride film 109, and the opening is provided with a polysilicon emitter electrode 111 and an emitter layer 110 therein.
The manufacturing method of the above-mentioned semiconductor device will be described in detail with reference to FIGS. 5A-5F. At first, the element-isolating oxide film 102 is formed on the silicon substrate 101 (see FIG. 5A). Subsequently, the epitaxial base region 103 thin crystal film having desired property and thickness is formed on the silicon substrate 101 by selective epitaxial growth (see FIG. 5B). Then, the buffer oxide film 105 is deposited by CVD (Chemical Vapor Deposition) on the upper surface of the epitaxial base region 103 (see FIG. 5C). The base extension polysilicon 104 is deposited thereon, and the oxide film 107 and the nitride film 108 are deposited on the base extension polysilicon 104 by CVD, in order. Then, an emitter opening is formed by conventional photolithography. On the sidewall of the opening, the sidewall nitride film 109 is formed. After forming a polysilicon emitter electrode 111 in the emitter opening, a heat treatment is performed to attain solid phase diffusion of impurity from the polysilicon emitter electrode 111 into the epitaxial base region 103 to form an emitter layer 110 in the epitaxial base region 103. In this manner, a complete bipolar transistor is obtained.
In the conventional manufacturing process of the bipolar transistor as mentioned above, however, a silicon epitaxial growth needs to be performed in the epitaxial base region 103, and thus the buffer oxide film 105 needs to be provided to protect the epitaxial base region 103 since a RIE (Reactive Ion Etching) apparatus is used in the forming process of the emitter layer 110. In addition thereto, a photoresist step needs to be performed in forming the buffer oxide film 105. Further, in order to attain a desired alignment precision, and the epitaxial base region 103 thus needs to be formed larger than the region in which the buffer oxide film 105 is formed.
Moreover, the semiconductor device obtained by the actual manufacturing process does not have a planar surface, and thus is not sufficiently downsized, as desired. Further, the base extension polysilicon has not been formed from silicide according to the conventional techniques, and thus the increase in the operation speed by the reduction of the resistance of the electrode, which is attained by forming the base from silicide, cannot have been attained.